Semiconductor integrated circuit device and method of producing the same

ABSTRACT

A semiconductor integrated circuit device includes a substrate, a nonvolatile memory device formed in a memory cell region of the substrate, and a semiconductor device formed in a device region of the substrate. The nonvolatile memory device has a multilayer gate electrode structure including a tunnel insulating film and a floating gate electrode formed thereon. The floating gate electrode has sidewall surfaces covered with a protection insulating film. The semiconductor device has a gate insulating film and a gate electrode formed thereon. A bird&#39;s beak structure is formed of a thermal oxide film at an interface of the tunnel insulating film and the floating gate electrode, the bird&#39;s beak structure penetrating into the floating gate electrode along the interface from the sidewall faces of the floating gate electrode, and the gate insulating film is interposed between the substrate and the gate electrode to have a substantially uniform thickness.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a Divisional application of U.S. applicationSer. No. 12/285,289, filed Oct. 1, 2008, which is a Divisional of U.S.application Ser. No. 10/083,533, filed on Feb. 27, 2002 which is basedon Japanese priority application No. 2001-205188 filed on Jul. 5, 2001,the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to semiconductor integratedcircuit devices and methods of producing the same, and more particularlyto a semiconductor integrated circuit device including a nonvolatilesemiconductor storage device and using a plurality of supply voltages,and a method of producing such a semiconductor integrated circuitdevice.

A flash memory device is a nonvolatile semiconductor storage device thatstores information in the form of electric charges in floating gateelectrodes. The flash memory device, which has a simple deviceconfiguration, is suitable for forming a large-scale integrated circuitdevice.

In the flash memory device, information is written or erased byinjecting hot carriers into and extracting hot carriers by theFowler-Nordheim-type tunnel effect from the floating gate electrodesthrough a tunnel insulating film. Since a high voltage is required togenerate such hot carriers, the flash memory device has a voltage risecontrol circuit that raises a supply voltage provided in its peripheralcircuits cooperating with memory cells. Therefore, transistors used insuch peripheral circuits have to operate at a high voltage.

On the other hand, it has been practiced of late to form such a flashmemory device and a high-speed logic circuit on a common semiconductorsubstrate as a semiconductor integrated circuit device. In such ahigh-speed logic circuit, a transistor employed therein is required tooperate at a low voltage. Therefore, such a semiconductor integratedcircuit device is required to use a plurality of supply voltages.

2. Description of the Related Art

FIGS. 1A through 1Q are diagrams showing a production process of theconventional semiconductor integrated circuit device including such aflash memory and using a plurality of supply voltages.

In FIG. 1A, a flash memory cell region A, a low-voltage operationtransistor region B, and a high-voltage operation transistor region Care formed in partitions on a silicon (Si) substrate 11 on which a fieldoxide film or an isolation structure (not shown in the drawing) such asa shallow trench isolation (STI) structure is formed. In the step ofFIG. 1A, a tunnel oxide film 12A of a thickness of 8 to 10 nm is formedon the above-described regions A through C by performing thermaloxidation on the surface of the Si substrate 11 at temperatures rangingfrom 800 to 1100° C. In the step of FIG. 1B, an amorphous silicon film13 doped with phosphorous (P) and having a thickness of 80 to 120 nm andan insulating film 14 having a so-called oxide-nitride-oxide (ONO)structure are successively deposited on the tunnel oxide film 12A. TheONO insulating film 14 is formed of a silicon dioxide (SiO₂) film 14 cof a thickness of 5 to 10 nm deposited by chemical vapor deposition(CVD) on the amorphous silicon film 13, a silicon nitride (SiN) film 14b of a thickness of 5 to 10 nm deposited by CVD on the SiO₂ film 14 c,and a thermal oxide film 14 a of a thickness of 3 to 10 nm formed on thesurface of the SiN film 14 b. The ONO insulating film 14 has a goodleakage-current characteristic.

Next, in the step of FIG. 1C, a resist pattern 15A is formed on theflash memory cell region A, and the ONO insulating film 14, theamorphous silicon film 13, and the tunnel oxide film 12A are removedfrom the low-voltage operation transistor region B and the high-voltageoperation transistor region C on the Si substrate 11 by using the resistpattern 15A as a mask so that the surface of the Si substrate 11 isexposed in the regions B and C. In removing the tunnel oxide film 12A,wet etching using hydrofluoric acid (HF) is performed so that thesurface of the Si substrate 11 is exposed to the HF in the regions B andC.

In the step of FIG. 1D, the resist pattern 15A is removed, and a thermaloxide film 12C of a thickness of 10 to 50 nm is formed in the regions Band C to cover the Si substrate 11 by performing thermal oxidation attemperatures ranging from 800 to 1100° C. The thermal oxide film 12C maybe replaced by a thermal nitride oxide film.

In the step of FIG. 1E, another resist pattern 15B is formed in theflash memory cell region A to cover the ONO insulating film 14 and inthe high-voltage operation transistor region C to cover the thermaloxide film 12C, and the thermal oxide film 12C is removed from thelow-voltage operation transistor region B by HF processing by using theresist pattern 15B as a mask so that the surface of the Si substrate 11is exposed in the region B. By the step of FIG. 1E, the surface of theSi substrate 11 is subjected to the second HF processing in the regionB.

In the step of FIG. 1F, the resist pattern 15B is removed, and a thermaloxide film 12B of a thickness of 3 to 10 nm is formed on the exposed Sisubstrate 11 in the region B by performing thermal oxidation attemperatures ranging from 800 to 1100° C. The thermal oxide film 12B maybe replaced by a thermal nitride oxide film. Further, in the step ofFIG. 1F, as a result of the thermal oxidation for forming the thermaloxide film 12B, the thickness of the thermal oxide film 12C formed inthe high-voltage operation transistor region C increases.

Next, in the step of FIG. 1G, an amorphous silicon film 16 doped with Pand having a thickness of 100 to 250 nm is deposited on the structure ofFIG. 1F by plasma CVD. The amorphous silicon film 16 may be replaced bya polysilicon film. Further, the amorphous silicon film 16 may be dopedwith P in a later step. In the step of FIG. 1H, a resist pattern 17A isformed on the amorphous silicon film 16, and by using the resist pattern17A as a mask, patterning is performed successively on the amorphoussilicon film 16, the ONO insulating film 14, and the amorphous siliconfilm 13 in the flash memory cell region A so that a multilayer gateelectrode structure 16F of the flash memory which structure is formed ofan amorphous silicon pattern 13A, an ONO pattern 14A, and an amorphoussilicon pattern 16A and includes the amorphous silicon pattern 13A as afloating gate electrode is formed in the region A. In the step of FIG.1G, it is possible to form a silicide film of, for instance, tungstensilicide (WSi) or cobalt silicide (CoSi) on the amorphous silicon film16 as required. Further, it is also possible to form a non-dopedpolysilicon film and then form an n-type gate electrode of P or arsenic(As) or a p-type gate electrode of boron (B) or difluoroboron (BF₂) in alater step of ion implantation.

Next, in the step of FIG. 1I, the resist pattern 17A is removed, and anew resist pattern 17B is formed to cover the flash memory cell regionA. By using the resist pattern 17B as a mask, patterning is performed onthe amorphous silicon film 16 in the low-voltage operation transistorregion B and the high-voltage operation transistor region C so that agate electrode 16B of a low-voltage operation transistor and a gateelectrode 16C of a high-voltage operation transistor are formed in theregions B and C, respectively.

Next, in the step of FIG. 1J, the resist pattern 17B is removed, and aprotection oxide film (also referred to as a protection insulating filmor a thermal oxide film) 18 is formed, by performing thermal oxidationat temperatures ranging from 800 to 900° C., to cover each of themultilayer gate electrode structure 16F in the flash memory cell regionA, the gate electrode 16B in the low-voltage operation transistor regionB, and the gate electrode 16C in the high-voltage operation transistorregion C.

Next, in the step of FIG. 1K, a resist pattern 19A is formed on thestructure of FIG. 1J so as to cover the low-voltage operation transistorregion B, the high-voltage operation transistor region C, and a part ofthe flash memory cell region A. By using the resist pattern 19A and themultilayer gate electrode structure 16F as masks, ion implantation of P⁺is performed typically with a dose of 1×10¹⁴ to 3×10¹⁴ cm⁻² ataccelerating voltages ranging from 30 to 80 keV so that an n-typediffusion region 11 a is formed next to the multilayer gate electrodestructure 16F in the Si substrate 11. P⁺ may be replaced by As⁺.

In the step of FIG. 1K, by using the resist pattern 19A as a mask, ionimplantation of As⁺ is performed typically with a dose of 1×10¹⁵ to6×10¹⁵ cm⁻² at accelerating voltages ranging from 30 to 50 keV so thatanother n-type diffusion region 11 b is formed inside the n-typediffusion region 11 a. In the step of FIG. 1K, no ion implantation isperformed in the low-voltage operation transistor region B and thehigh-voltage operation transistor region C since the regions B and C arecovered with the resist pattern 19A.

Next, in the step of FIG. 1L, the resist pattern 19A is removed, and anew resist pattern 19B is formed to cover the regions B and C and leavethe region A exposed. Further, in the step of FIG. 1L, by using theresist pattern 19B as a mask, ion implantation of As⁺ is performed witha dose of 5×10¹⁴ to 5×10¹⁵ cm⁻² at accelerating voltages ranging from 30to 50 keV. As may be replaced by P⁺. As a result, an impurityconcentration is increased in the n-type diffusion region 11 b and atthe same time, a yet another n-type diffusion region 11 c is formed inthe flash memory cell region A by using the multilayer gate electrodestructure 16F as a self-alignment mask. At this point, the step of FIG.1K may be deleted.

Next, in the step of FIG. 1M, the resist pattern 19B is removed, and aresist pattern 19C is formed on the Si substrate 11 so as to leave onlythe low-voltage operation transistor region B exposed. Further, in thestep of FIG. 1M, ion implantation of a p-type or n-type impurity isperformed by using the resist pattern 19C as a mask so that a pair oflightly doped drain (LDD) diffusion regions 11 d are formed on bothsides of the gate electrode 16B in the Si substrate 11 in the region Bwith the gate electrode 16B serving as a self-alignment mask.

Next, in the step of FIG. 1N, the resist pattern 19C is removed, and aresist pattern 19D is formed on the Si substrate 11 so as to leave onlythe high-voltage operation transistor region C exposed. Further, in thestep of FIG. 1N, ion implantation of a p-type or n-type impurity elementis performed by using the resist pattern 19D as a mask so that a pair ofLDD diffusion regions 11 e are formed on both sides of the gateelectrode 16C in the Si substrate 11 in the region C. The diffusionregions 11 d and 11 e may be formed in the same step.

Further, in the step of FIG. 1O, sidewall insulating films 16 s areformed on both sides of each of the multilayer gate electrode structure16F, the gate electrode 16B, and the gate electrode 16C by depositingand performing etchback on a CVD oxide film. In the step of FIG. 1P, aresist pattern 19E is formed to cover the flash memory cell region A andleave the low-voltage operation transistor region B and the high-voltageoperation transistor region C exposed. Further, by performing ionimplantation of a p-type or n-type impurity element with the resistpattern 19E and the gate electrodes B and C serving as a mask, p-type orn-type diffusion regions 11 f are formed on both sides of the gateelectrode 16B in the Si substrate 11 in the region B, and similarly,p-type or n-type diffusion regions 11 g are formed on both sides of thegate electrode 16C in the Si substrate 11 in the region C. Alow-resistance silicide film of, for instance, WSi or CoSi may be formedas required on the surface of each of the diffusion regions 11 f and 11g by silicide processing.

In the step of FIG. 1Q, an interlayer insulating film 20 is formed onthe Si substrate 11 so as to continuously cover the regions A through C.Further, in the region A, contact holes are formed in the interlayerinsulating film 20 so that the diffusion regions 11 b and 11 c areexposed, and W plugs 20A are formed in the contact holes. Likewise, inthe region B, contact holes are formed in the interlayer insulating film20 so that the diffusion regions 11 f are exposed, and W plugs 20B areformed in the contact holes. In the region C, contact holes are formedin the interlayer insulating film 20 so that the diffusion regions 11 gare exposed, and W plugs 20C are formed in the contact holes.

In the production process of the semiconductor integrated circuit deviceincluding the flash memory device having the multilayer gate electrodestructure 16F, in the step of FIG. 1J, the protection oxide film 18 of athickness of 5 to 10 nm is formed on the sidewall faces of themultilayer gate electrode structure 16F by thermal oxidation performedat temperatures ranging from 800 to 900° C. As a result of the thermaloxidation, the protection oxide film 18 is formed not only on themultilayer gate electrode structure 16F but also on the sidewall facesof each of the gate electrode 16B formed in the low-voltage operationtransistor region B and the gate electrode 16C formed in thehigh-voltage operation transistor region C as shown in FIGS. 2A and 2B.

At this point, the protection oxide film 18 forms bird's beaks thatpenetrate under the gate electrode 16B in the region B as shown circledby broken lines in FIG. 2B. Therefore, especially in a low-voltageoperation transistor whose gate length is short, that is, whose gateoxide film 12B is thin, a substantial change in the thickness of thegate oxide film 12B is effected right under the gate electrode 16B, thuscausing a problem that a threshold characteristic shifts from a desiredvalue.

Indeed, such a problem is prevented from occurring if the protectionoxide film 18 is not formed. However, without formation of theprotection oxide film 18, electrons retained in the amorphous siliconpattern 13A (hereinafter, also referred to as a floating gate electrodepattern 13A) are dissipated to the sidewall insulating films 16 s formedby CVD and etchback in the step of FIG. 1O as shown in FIG. 3B so thatinformation stored in the flash memory device is lost in a short periodof time. On the other hand, with the protection oxide film 18 that is ahigh-quality thermal oxide film hardly allowing a leakage current beingformed on the sidewalls of the floating gate electrode pattern 13A, theelectrons injected into the floating gate electrode pattern 13A arestably retained therein as shown in FIG. 3A.

Therefore, it is essential to form the protection oxide film 18 in thesemiconductor integrated circuit device including the flash memorydevice. However, formation of such a protection oxide film inevitablycauses the problem of a change in the threshold characteristic of a MOStransistor forming a peripheral or logic circuit. Such a problem of achange in the threshold characteristic of the MOS transistor isnoticeable when the MOS transistor is a high-speed transistor having ashort gate length.

FIG. 4 is a plan view of a configuration of a flash memory cell (flashmemory device) having a single-layer gate electrode structure by relatedart. In FIG. 4, the same element as those of the previous drawings arereferred to by the same numerals, and a description thereof will beomitted.

According to FIG. 4, a device region 11A is formed on the Si substrate11 by a field oxide film 11F. One end of the above-described floatinggate electrode pattern 13A is formed on the Si substrate 11 to cross thedevice region 11A. In the device region 11A, by using the floating gateelectrode pattern 13A as a self-alignment mask, the n⁻-type sourceregion 11 a and the n⁺-type source line region 11 b are formed on oneside, and the n⁺-type drain region 11 c is formed on the other side.

On the Si substrate 11, another device region 11B is formed next to thedevice region 11A. An n⁺-type diffusion region 11C is formed in thedevice region 11B. The other end of the floating gate electrode pattern13A is formed as a coupling part 13Ac covering the diffusion region 11C.

FIG. 5A is a sectional view of the flash memory cell of FIG. 4 takenalong the line X-X′.

According to FIG. 5A, the tunnel oxide film 12A is formed between thesource line region 11 b and the drain region 11 c on the Si substrate11, and the floating gate electrode pattern 13A is formed on the tunneloxide film 12A. Further, the n⁻-type source region 11 a is formedoutside the n⁺-type source line region 11 b in the Si substrate 11. Thesidewall insulating films 16 s are formed on the sidewalls of thefloating gate electrode pattern 13A.

FIG. 5B is a sectional view of the flash memory cell of FIG. 4 takenalong the line Y-Y′.

According to FIG. 5B, the floating gate electrode pattern 13Acontinuously extends from the device region 11A to the adjacent deviceregion 11B on the field oxide film 11F formed on the Si substrate 11.The coupling part 13Ac of the floating gate electrode pattern 13A iscapacitive-coupled via an oxide film 12Ac to the high-density diffusionregion 11C.

At the time of a write (program) operation, by providing the source lineregion 11 b, applying a drain voltage of +5 V to the drain region 11 c,and applying a write voltage of +10 V to the high-density diffusionregion 11C as shown in FIGS. 6A and 6B, the potential of the floatinggate electrode pattern 13A rises so that hot electrons are injected intothe floating gate electrode pattern 13A via the tunnel oxide film 12A inthe device region 11A.

On the other hand, at the time of an erase operation, an erase voltageof +15 V is applied to the source line region 11 b with the drain region11 c and the high-density diffusion region 11C being grounded as shownin FIGS. 6C and 6D. As a result, the electrons in the floating gateelectrode pattern 13A tunnel through the tunnel oxide film 12A to thesource region 11 a to be absorbed into a source power supply through thesource line region 11 b.

Thus, in the flash memory cell of FIG. 4, the high-density diffusionregion 11C serves as a control gate electrode, and unlike theconventional flash memory cell of a multilayer gate structure, it isunnecessary to form the above-described ONO insulating film 14 betweenthe polysilicon floating gate electrode and the polysilicon control gateelectrode. In the flash memory cell of FIGS. 5A and 5B, the oxide film12Ac serves as the ONO insulating film 14. Since the oxide film 12Ac isformed on the Si substrate 11 by thermal oxidation, the oxide film 12Achas high quality.

FIGS. 7A through 7M are diagrams showing a production process of asemiconductor integrated circuit device including the flash memory cellof FIG. 4 in addition to the low-voltage operation transistor B and thehigh-voltage operation transistor C. In the drawings, the same elementsas those previously described are referred to by the same numerals, anda description thereof will be omitted.

According to FIG. 7A, the thermal oxide film 12C of a thickness of 5 to50 nm is formed on the Si substrate 11 by performing thermal oxidationat temperatures ranging from 800 to 1100° C. in each of the flash memorycell region A, the low-voltage operation transistor region B, and thehigh-voltage operation transistor region C. In the step of FIG. 15B, thethermal oxide film 12C is removed from the flash memory cell region A bya patterning process using a resist pattern 15 ₁.

Next, in the step of FIG. 7C, the resist pattern 15 ₁ is removed, andthe tunnel oxide film 12A of a thickness of 5 to 15 nm is formed on thesurface of the Si substrate 11 in the region A by performing thermaloxidation at temperatures ranging from 800 to 1100° C. In the step ofFIG. 7C, as a result of the thermal oxidation for forming the tunneloxide film 12A, the thermal oxide film 12C is developed in each of theregions B and C.

Next, in the step of FIG. 7D, the thermal oxide film 12C is removed fromthe low-voltage operation transistor region B by a patterning processusing a resist pattern 15 ₂. Then, in the step of FIG. 7E, after theresist pattern 15 ₂ is removed, the thermal oxide film 12B of athickness of 3 to 10 nm is formed on the exposed Si substrate 11 in theregion B by performing thermal oxidation at temperatures ranging from800 to 1100° C. In the step of FIG. 7E, as a result of the thermaloxidation for forming the thermal oxide film 12B, the tunnel oxide film12A is developed in the region A and the thermal oxide film 12C isdeveloped in the region C.

Next, in the step of FIG. 7F, the amorphous silicon film 13 uniformlydoped with P and having a thickness of 150 to 200 nm is formed on the Sisubstrate 11. In the step of FIG. 7G, patterning is performed on theamorphous silicon film 13 with a resist pattern 17 ₁ serving as a mask,so that the floating gate electrode pattern 13A is formed in the flashmemory cell region A, a gate electrode pattern 13B is formed in thelow-voltage operation transistor region B, and a gate electrode pattern13C is formed in the high-voltage operation transistor region C.

Next, in the step of FIG. 7H, the surfaces of the floating gateelectrode pattern 13A and the gate electrode patterns 13B and 13C arecovered with the protection oxide film 18 of a thickness of 5 to 10 nmby thermal oxidation at temperatures ranging from 800 to 900° C. Then,in the step of FIG. 7I, with a resist pattern 17 ₂ serving as a mask,the source region 11 a is formed by performing ion implantation of P⁺ orAs⁺ with a dose of 1×10¹⁴ to 5×10¹⁴ cm⁻² at accelerating voltagesranging from 30 to 80 keV.

Further, in the step of FIG. 7J, with the regions B and C being coveredwith a resist pattern 17 ₃, ion implantation of As⁺ is performed with adose of 5×10¹⁴ to 3×10¹⁵ cm⁻² at accelerating voltages ranging from 30to 50 keV in the region A by using the floating gate electrode pattern13A as a self-alignment mask. Thereby, the n⁺-type source line region 11b is formed inside the source region 11 a and the n⁺-type drain region11 c is formed on the opposite side of a channel region from the sourceregion 11 a.

Next, in the step of FIG. 7K, a resist pattern 17 ₃ covering the flashmemory cell region A is formed, and the LDD regions 11 d and 11 e areformed in the regions B and C, respectively, by ion implantation of ap-type or n-type impurity element.

Further, in the step of FIG. 7L, the sidewall oxide films 16 s areformed on both sidewalls of each of the floating gate electrode pattern13A and the gate electrode patterns 13B and 13C. In the step of FIG. 7M,with the flash memory region A being covered with a resist pattern 17 ₄,the diffusion regions 11 f and 11 g are formed in the regions B and C,respectively, by ion implantation of a p-type or n-type impurityelement.

Also in the production of the semiconductor integrated circuit deviceincluding the flash memory device of such a single-layer gate structure,when the thermal oxide film 18 is formed as a protection insulating filmto cover the single-layer gate electrode structure (the floating gateelectrode pattern) 13A in the flash memory cell region A as shown indetail in FIG. 8A in the step of FIG. 7H, the same thermal oxide film 18is also formed in the low-voltage transistor region B so as to cover thegate electrode 13B as shown in FIG. 8B. As a result, bird's beaks thatpenetrate right under the gate electrode 13B are formed as shown circledin FIG. 8B. Therefore, the low-voltage operation transistor formed inthe region B is prevented from having a desired thresholdcharacteristic.

SUMMARY OF THE INVENTION

It is a general object of the present invention to provide asemiconductor integrated circuit device and a method of producing thesame in which the above-described disadvantage is eliminated.

A more specific object of the present invention is to provide asemiconductor integrated circuit device in which formation of bird'sbeak right under the gate electrode of a semiconductor device formedtogether with a flash memory device on a substrate is effectivelyprevented.

Yet another object of the present invention is to provide a method ofproducing such a semiconductor integrated circuit device.

The above objects of the present invention are achieved by asemiconductor integrated circuit device including a substrate, anonvolatile memory device formed in a memory cell region of thesubstrate and having a multilayer gate electrode structure including atunnel insulating film covering the substrate and a floating gateelectrode formed on the tunnel insulating film and having sidewallsurfaces covered with a protection insulating film formed of a thermaloxide film, and a semiconductor device formed in a device region of thesubstrate, the semiconductor device including a gate insulating filmcovering the substrate and a gate electrode formed on the gateinsulating film, wherein a bird's beak structure is formed of a thermaloxide film at an interface of the tunnel insulating film and thefloating gate electrode, the bird's beak structure penetrating into thefloating gate electrode along the interface from the sidewall faces ofthe floating gate electrode, and the gate insulating film is interposedbetween the substrate and the gate electrode to have a substantiallyuniform thickness.

The above objects of the present invention are also achieved by asemiconductor integrated circuit device including: a substrate; anonvolatile memory device formed in a memory cell region of thesubstrate, the nonvolatile memory device including a first active regioncovered with a tunnel insulating film, a second active region formednext to the first active region and covered with an insulating film, acontrol gate formed of an embedded diffusion region formed in the secondactive region, a first gate electrode extending on the tunnel insulatingfilm in the first active region and forming a bridge between the firstand second active regions to be capacitive-coupled via the insulatingfilm to the embedded diffusion region in the second active region, thefirst gate electrode having sidewall faces thereof covered with aprotection insulating film formed of a thermal oxide film, and adiffusion region formed on each of sides of the first gate electrode inthe first active region; and a semiconductor device formed in a deviceregion of the substrate, the semiconductor device including a gateinsulating film covering the substrate and a second gate electrodeformed on the gate insulating film, wherein a bird's beak structure isformed of a thermal oxide film at an interface of the tunnel insulatingfilm and the first gate electrode, the bird's beak structure penetratinginto the first gate electrode along the interface from the sidewallfaces of the first gate electrode, and the gate insulating film isinterposed between the substrate and the second gate electrode to have asubstantially uniform thickness.

According to the above-described semiconductor integrated circuitdevices, no bird's beak structure is formed to penetrate into the secondgate electrode. Therefore, the problem of a change in the thresholdcharacteristic of the semiconductor device can be avoided.

The above objects of the present invention are also achieved by a methodof producing a semiconductor integrated circuit device, including thesteps of (a) forming a semiconductor structure including a tunnelinsulating film covering a memory cell region of a substrate, a firstsilicon film covering the tunnel insulating film, an insulating filmcovering the first silicon film, and a gate insulating film covering alogic device region of the substrate, (b) depositing a second siliconfilm on the semiconductor structure formed in the step (a) so that thesecond silicon film covers the insulating film in the memory cell regionand the gate insulating film in the logic device region, (c) forming amultilayer gate electrode structure in the memory cell region bysuccessively patterning the second silicon film to serve as a controlgate electrode, the insulating film, and the first silicon film in thememory cell region with the second silicon film being left in the logicdevice region, (d) forming a protection oxide film so that theprotection oxide film covers the multilayer gate electrode structure inthe memory cell region and the second silicon film in the logic deviceregion, (e) forming diffusion regions in both sides of the multilayergate electrode structure in the memory cell region by performing ionimplantation of an impurity element into the substrate with themultilayer gate electrode structure and the second silicon film beingemployed as masks, (f) forming a gate electrode in the logic deviceregion by patterning the second silicon film, and (g) forming diffusionregions in the logic device region by performing ion implantation withthe gate electrode being employed as a mask, whereby a nonvolatilememory device is formed in the memory cell region and a semiconductordevice is formed in the logic device region.

The above objects of the present invention are further achieved by amethod of producing a semiconductor integrated circuit device, includingthe steps of (a) forming a semiconductor structure including a tunnelinsulating film covering a memory cell region of a substrate and a gateinsulating film covering a logic device region of the substrate, (b)depositing a silicon film on the semiconductor structure formed in thestep (a) so that the silicon film covers the tunnel insulating film inthe memory cell region and the gate insulating film in the logic deviceregion, (c) forming a first gate electrode in the memory cell region byselectively patterning the silicon film with the silicon film being leftin the logic device region, (d) forming a protection oxide film so thatthe protection oxide film covers the first gate electrode in the memorycell region and the silicon film in the logic device region, (e) formingdiffusion regions on both sides of the first gate electrode in thememory cell region by performing ion implantation of an impurity elementinto the substrate with the first gate electrode and the silicon filmbeing employed as masks, (f) forming a second gate electrode in thelogic device region by patterning the silicon film, and (g) formingdiffusion regions in the logic device region by performing ionimplantation with the second gate electrode being employed as a mask,whereby a nonvolatile memory device is formed in the memory cell regionand a semiconductor device is formed in the logic device region.

According to the above-described methods, the protection oxide film isformed to cover the multilayer gate electrode structure or the gateelectrode in the memory cell region before the gate electrode ispatterned in the logic device region. The protection oxide film preventsthe bird' beak structure from being formed as a penetration into thegate electrode in the logic device region. Therefore, the problem of achange in the threshold characteristic of the semiconductor device inthe device region can be avoided. Further, when the diffusion regionsare formed in the memory cell region by ion implantation, the deviceregion is covered with the silicon film. By using the silicon film as amask, a resist process may be omitted, thus simplifying the productionprocess of the semiconductor integrated circuit device.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects, features and advantages of the present invention willbecome more apparent from the following detailed description when readin conjunction with the accompanying drawings, in which:

FIGS. 1A through 1Q are diagrams showing a production process of aconventional semiconductor integrated circuit device including a flashmemory device of a multilayer gate structure;

FIGS. 2A and 2B are diagrams for illustrating a disadvantage of theconventional semiconductor integrated circuit device including the flashmemory device of the multilayer gate structure;

FIGS. 3A and 3B are diagrams for illustrating a role of a protectionoxide film employed in the flash memory device of the multilayer gatestructure employed in the conventional semiconductor integrated circuitdevice;

FIG. 4 is a plan view of a flash memory cell of a single-layer gatestructure according to related art;

FIGS. 5A and 5B are sectional views of the flash memory cell of FIG. 4;

FIGS. 6A through 6D are diagrams for illustrating write and eraseoperations of the flash memory cell of FIG. 4;

FIGS. 7A through 7M are diagrams showing a production process of asemiconductor integrated circuit device including the flash memory cellof FIG. 4

FIGS. 8A and 8B are diagrams for illustrating a disadvantage of thesemiconductor integrated circuit device including the flash memory cellof FIG. 4;

FIGS. 9A through 9I are diagrams showing a production process of asemiconductor integrated circuit device according to a first embodimentof the present invention;

FIGS. 10A and 10B are diagrams for illustrating an effect of the firstembodiment;

FIGS. 11A and 11B are diagrams for illustrating another effect of thefirst embodiment;

FIGS. 12A through 12I are diagrams showing a production process of asemiconductor integrated circuit device according to a second embodimentof the present invention; and

FIGS. 13A and 13B are diagrams for illustrating effects of the secondembodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A description will now be given, with reference to the accompanyingdrawings, of embodiments of the present invention.

First Embodiment

FIGS. 9A through 9I are diagrams showing a production process of asemiconductor integrated circuit device according to a first embodimentof the present invention. In the drawings, the same elements as thosepreviously described are referred to by the same numerals, and adescription thereof will be omitted.

In this embodiment, the steps of FIGS. 1A through 1G are firstperformed, so that a structure corresponding to FIG. 1G is obtained inthe step of FIG. 9A. At this point, a silicon-on-insulator (SOI)substrate may replace the Si substrate 11. Further, a tunnel nitridefilm may replace the tunnel oxide film 12A.

Further, in the step of FIG. 9B, the multilayer gate electrode structure16F is formed in the flash memory cell region A by performing patterningusing the resist pattern 17A described in the step of FIG. 1H. In thestep of FIG. 9B, no patterning is performed on the low-voltage operationtransistor region B and the high-voltage operation transistor region Cthat are covered with the resist pattern 17A.

In this embodiment, next, in the step of FIG. 9C, the resist pattern 17Ais removed, and the protection insulating film 18 is formed of a thermaloxide film to cover the multilayer gate electrode structure 16F byperforming thermal oxidation at temperatures ranging from 800 to 900° C.The same thermal oxide film 18 is also formed on the surface of theamorphous silicon film 16 in each of the regions B and C.

Further, in the step of FIG. 9C, with the multilayer gate electrodestructure 16F serving as a self-alignment mask, the diffusion region 11c is formed in the flash memory cell region A by performing ionimplantation of As⁺ (or P⁺) under the same conditions as in theabove-described step of FIG. 1L. The impurity concentration may be thesame on the side of the diffusion regions 11 a and 11 b and the side ofthe diffusion region 11 c. At this point, no ion is injected into the Sisubstrate 11 in the regions B and C that are covered with the amorphoussilicon film 16. A resist pattern that has an opening on the flashmemory cell region A may be employed.

In the step of FIG. 9D, by using the resist pattern 17B previouslydescribed in the step of FIG. 1I as a mask, patterning is performed onthe amorphous silicon film 16 in the regions B and C so that the gateelectrodes 16B and 16C are formed in the low-voltage operationtransistor region B and the high-voltage operation transistor region C,respectively.

Next, in the step of FIG. 9E, with the resist pattern 19C previouslydescribed in the step of FIG. 1M being employed as a mask, the LDDdiffusion regions 11 d are formed in the Si substrate 11 in the region Bby performing ion implantation of an n-type or p-type impurity elementtherein.

In the step of FIG. 9F, with the resist pattern 19D previously describedin the step of FIG. 1N being employed as a mask, the LDD diffusionregions 11 e are formed in the Si substrate 11 in the region C byperforming ion implantation of an n-type or p-type impurity elementtherein. In the steps of FIGS. 9E and 9F, the diffusion regions 11 d and11 e may be formed under the same ion implantation conditions in thesame step.

In the step of FIG. 9G, which corresponds to the above-described step ofFIG. 1O, the sidewall insulating films 16 s are formed on each of themultilayer gate electrode structure 16F and the gate electrodes 16B and16C. In the step of FIG. 9H, which corresponds to the above-describedstep of FIG. 1P, the flash memory cell region A is covered with theresist pattern 19E. Further, with the gate electrodes 16B and 16C andthe sidewall insulating films 16 s being used as self-alignment masks,the diffusion regions 11 f and 11 g are formed in the Si substrate 11 inthe regions B and C, respectively, by performing ion implantation of ann-type or p-type impurity element therein.

Further, by performing the same step as previously described in FIG. 1Q,a semiconductor integrated circuit device of the structure of FIG. 9Icorresponding to FIG. 1Q can be obtained.

In this embodiment, when the protection insulating film 18 is formed bythermal oxidation in the step of FIG. 9C, no patterning has beenperformed on the amorphous silicon film 16 in the regions B and C. As aresult, in the regions B and C, the thermal oxide film 18 is formed onthe surface of the amorphous silicon film 16, but is prevented frombeing formed at an interface between the amorphous silicon film 16 andthe gate oxide film 12B. Further, no such thermal oxidation is performedin any step after the patterning step of the gate electrodes 16B and 16Cof FIG. 9D. Therefore, although the protection insulating film 18 isformed to cover the multilayer gate electrode structure 16F as shown inFIG. 10A, no thermal oxide film other than the gate oxide film 12B isdeveloped on the bottom of the gate electrode 16B. Therefore, theproblem of a change in the threshold characteristic of the low-voltageoperation transistor can be avoided.

As shown circled in FIG. 10A, in the step of FIG. 9C, bird's beaks areformed under the floating gate electrode pattern 13A with the formationof the protection insulating film 18. On the other hand, with respect tothe MOS transistors of the regions B and C, bird's beaks, if everformed, are far smaller in thickness and penetration distance than thoseformed under the floating gate electrode pattern 13A.

Further in this embodiment, as shown in FIGS. 11A and 11B, in the ionimplantation step of FIG. 9C, no resist pattern is required to beprovided in the low-voltage operation transistor region B and thehigh-voltage operation transistor region C since the regions B and C arecovered with the amorphous silicon film 16. Consequently, thissimplifies the production process of the semiconductor integratedcircuit device.

Second Embodiment

FIGS. 12A through 12I are diagrams showing a production method of asemiconductor integrated circuit device including a flash memory deviceof a single-layer gate electrode structure according to a secondembodiment of the present invention. In the drawings, the same elementsas those previously described are referred to by the same numerals, anda description thereof will be omitted.

In this embodiment, steps corresponding to those of FIGS. 7A through 7Dare first performed, so that a structure corresponding to that of FIG.7E is obtained in the step of FIG. 12A. In this embodiment, an SOIsubstrate may also replace the Si substrate 11. Further, a thermalnitride oxide film may replace the tunnel oxide film 12A or the thermaloxide films 12B and 12C.

Next, in the step of FIG. 12B, which corresponds to the step of FIG. 7F,the amorphous silicon film 13 of a thickness of 100 to 300 nm isdeposited on the structure of FIG. 12A. The amorphous silicon film 13may be replaced by a polysilicon film. Further, the amorphous siliconfilm 13 may be doped with P⁺. In the step of FIG. 12C, patterning isperformed on the amorphous silicon film 13 by using a resist pattern 27₁ as a mask so that the floating gate electrode pattern 13A is formed.The resist pattern 27 ₁ covers the low-voltage operation transistorregion B and the high-voltage operation transistor region C.Consequently, no patterning is performed on the amorphous silicon film13 in the regions B and C in the step of FIG. 12C.

Next, in the step of FIG. 12D, the resist pattern 27 ₁ is removed, andthe protection insulating film 18 of a thickness of 5 to 10 nm is formedof a thermal oxide film so as to cover the floating gate electrodepattern 13A in the region A by performing thermal oxidation attemperatures ranging from 800 to 900° C. As a result of the thermaloxidation, the thermal oxide film 18 is also formed on the surface ofthe amorphous silicon film 13 in the regions B and C.

Next, in the step of FIG. 12E, a resist pattern 27 ₂ corresponding tothe resist pattern 17 ₂ in FIG. 7I is formed on the structure of FIG.12D. With the resist pattern 27 ₂ being employed as a mask, ionimplantation of P⁺ (or As⁺) is performed with a dose of 1×10¹⁴ to 5×10¹⁴cm⁻² at accelerating voltages ranging from 30 to 80 keV so that thediffusion region 11 a is formed next to the floating gate electrodepattern 13A in the flash memory cell region A. Further in the step ofFIG. 12E, after the ion implantation of P⁺, ion implantation of As⁺ isperformed with a dose of 1×10¹⁵ to 6×10¹⁵ cm⁻² at accelerating voltagesranging from 30 to 80 keV so that the resistance of the diffusion region11 a is reduced.

Next, in the step of FIG. 12F, the resist pattern 27 ₂ is removed, andwith the floating gate electrode pattern 13A being employed as a mask,ion implantation of As⁺ is performed with a dose of 5×10¹⁴ to 3×10¹⁵cm⁻² at accelerating voltages ranging from 20 to 60 keV in the region Aso that the diffusion regions 11 b and 11 c are formed in the Sisubstrate 11 in the region A. At this point, the step of FIG. 12E isomittable. Further, a resist pattern having an opening only on the flashmemory cell region A may be formed alternatively.

Next, in the step of FIG. 12G, a resist pattern 27 ₃ is formed on thestructure of FIG. 12F. The flash memory cell region A is covered withthe resist pattern 27 ₃. Then, patterning is performed on the amorphoussilicon film 13 with the resist pattern 27 ₃ being employed as a mask inthe regions B and C so that the gate electrodes 13B and 13C are formedtherein.

In the step of FIG. 12H, the resist pattern 27 ₃ is removed and a resistpattern 27 ₄ covering the flash memory cell region A is formed. With theresist pattern 27 ₄ being employed as a mask, an n-type or p-typeimpurity element is introduced into the Si substrate 11 by ionimplantation so that the LDD diffusion regions 11 d and 11 e are formedin the regions B and C, respectively.

Further, in the step of FIG. 12I, the resist pattern 27 ₄ is removed,and a CVD oxide film 16S is deposited. Further, with the CVD oxide film16S being protected by a resist pattern 27 ₅ in the flash memory cellregion A, etchback is performed in the regions B and C so that thesidewall oxide films 16 s are formed on the sidewalls of each of thegate electrodes 13B and 13C.

Furthermore, by performing the same ion implantation as in the step ofFIG. 7M on the structure of FIG. 12I, the diffusion regions 11 f and 11g in the Si substrate 11. A p-type or n-type gate electrode is alsoformable. A low-resistance silicide film of, for instance, WSi or CoSimay be formed as required on the surface of each of the gate electrodes13B and 13C and the diffusion regions 11 f and 11 g by silicideprocessing.

FIGS. 13A and 13B are diagrams showing detailed configurations of theflash memory device and the low-voltage operation transistor formedaccording to this embodiment.

As shown in FIG. 13A, the floating gate electrode pattern 13A has notonly its sidewall faces but also its top surface uniformly covered withthe protection insulating film 18 in this embodiment. Therefore,electrons accumulated in the floating gate electrode pattern 13A arestably retained even if the flash memory device is left in a hotenvironment for a long time.

Further in this embodiment, the amorphous silicon film 13 is notpatterned in the regions B and C when the thermal oxidation step of FIG.12D is performed. Therefore, as shown in FIG. 13B, no bird' beaks of thethermal oxide film penetrate under the gate electrodes 13B and 13C. Thisstabilizes the threshold characteristic and the operation characteristicof each MOS transistor formed on the Si substrate 11 on which the flashmemory device is formed as well. The improvements in the thresholdcharacteristic and the operation characteristic are remarkable in alow-voltage operation transistor having a short gate length and a thingate oxide film.

In this embodiment, no resist pattern is required to be formed in theion implantation step of FIG. 12F, thus simplifying the productionprocess.

In the flash memory device of a multilayer-gate type according to theprevious embodiment, the multilayer gate electrode structure 16F mayalso have its sidewall faces and top surface covered continuously withthe protection insulating film 18 in the configuration of FIG. 9I as inthat of FIG. 12I.

According to the present invention, a protection oxide film is formed tocover a multilayer gate electrode structure or a floating gate electrodepattern in a flash memory cell region before a gate electrode ispatterned in a first or second device region. The protection oxide filmprevents a bird' beak structure from being formed to penetrate into thegate electrode in the device region. Therefore, the problem of a changein the threshold characteristic of a semiconductor device in the deviceregion can be avoided. Further, according to the present invention, whendiffusion regions are formed in the flash memory cell region by ionimplantation, the device region is covered with an amorphous siliconfilm. By using the amorphous silicon film as a mask, a resist processmay be omitted, thus simplifying the production process.

The present invention is not limited to the specifically disclosedembodiments, but variations and modifications may be made withoutdeparting from the scope of the present invention.

1. A method of producing a semiconductor integrated circuit device,comprising the steps of: (a) forming a semiconductor structurecomprising a tunnel insulating film covering a memory cell region of asubstrate and a gate insulating film covering a logic device region ofthe substrate; (b) depositing a silicon film on the semiconductorstructure formed in said step (a) so that the silicon film covers thetunnel insulating film in the memory cell region and the gate insulatingfilm in the logic device region; (c) forming a first gate electrode inthe memory cell region by selectively patterning the silicon film withthe silicon film being left in the logic device region; (d) forming aprotection oxide film so that the protection oxide film covers the firstgate electrode in the memory cell region and the silicon film in thelogic device region; (e) forming diffusion regions on both sides of thefirst gate electrode in the memory cell region by performing ionimplantation of an impurity element into the substrate with the firstgate electrode and the silicon film being employed as masks; (f) forminga second gate electrode in the logic device region by patterning thesilicon film; and (g) forming diffusion regions in the logic deviceregion by performing ion implantation with the second gate electrodebeing employed as a mask, whereby a nonvolatile memory device is formedin the memory cell region and a semiconductor device is formed in thelogic device region.
 2. The method as claimed in claim 1, wherein thelogic device region comprises first and second device regions; said step(a) forms first and second gate insulating films in the first and seconddevice regions, respectively, the second insulating film being thickerthan the first insulating film; said step (f) forms third and fourthgate electrodes in the first and second device regions, respectively, bypatterning the second silicon film; and said step (g) forms diffusionregions in the first and second device regions by employing the thirdand fourth gate electrodes being employed as masks, respectively.
 3. Themethod as claimed in claim 2, wherein said step (b) is performedsimultaneously in the memory cell region and the first and second deviceregions.
 4. The method as claimed in claim 2, wherein each of the thirdand fourth gate electrodes comprises a polycide or polymetal structureincluding a silicon film doped with an n-type or p-type dopant.
 5. Themethod as claimed in claim 1, wherein said step (b) is performedsimultaneously in the memory cell region and the logic device region. 6.The method as claimed in claim 1, wherein said step (e) is performedwithout using a resist mask.
 7. The method as claimed in claim 1,wherein said step (a) employs a tunnel oxide film as the tunnelinsulating film.
 8. The method as claimed in claim 1, wherein said step(a) employs a tunnel nitride film as the tunnel insulating film.
 9. Themethod as claimed in claim 1, wherein a silicon-on-insulator substrateis employed as the substrate.
 10. The method as claimed in claim 1,wherein said step (d) forms the protection oxide film by thermaloxidation so that the protection oxide film is formed of a thermal oxidefilm.
 11. The method as claimed in claim 1, wherein said step (g)performs ion implantation with the memory cell region being protected bya resist mask.
 12. The method as claimed in claim 1, wherein the secondgate electrode comprises a polycide or polymetal structure including asilicon film doped with an n-type or p-type dopant.